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by IQAC KIITKIIT Deemed to be University — Internal Quality Assurance Cell

Publication2012

Design of high speed Vedic multiplier for decimal number system

The record

Type
Publication
Date
1 January 2012
Level
National
Journal
Lecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics
Volume
7373 LNCS
Pages
79-88
Published
1 January 2012
DOI
10.1007/978-3-642-31494-0_10
Scopus ID
84864314860
ISSN
03029743
Authors
4
Open access
No
Citations
12
International co-authorship
No
Co-author countries
IN

Classification

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UN Sustainable Development Goals

  1. 9.4 Upgrade infrastructure and retrofit industries to make them sustainable and resource-efficient

    TargetPrimaryModerate confidenceJudged

    Vedic multiplier circuit design demonstrates high-speed digital electronics innovation for decimal computation in VLSI applications

    Moderate confidence
    The alignment is plausible and defensible but rests on an assumption a reasonable reviewer could decline. Published, and surfaced in the review queue for a human to confirm or override.
    Judged
    Judged against the published classification rubric, under the rubric and prompt versions recorded with the run that produced it.
    Produced by
    claude-haiku-4-5-20251001, under kortex-publication-v1

Viksit Bharat @2047

  1. vb-3 Innovation, Science and Technology

    ThemePrimaryModerate confidenceJudged

    Derived through the seeded SDG-to-Viksit-Bharat crosswalk from the primary SDG 9 label. Vedic multiplier circuit design demonstrates high-speed digital electronics innovation for decimal computation in VLSI applications

    Produced by
    claude-haiku-4-5-20251001, under kortex-publication-v1

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KIIT Deemed to be University. “Design of high speed Vedic multiplier for decimal number system”. Kortex.

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